Verilog HDL JK 正反器(Flip-Flop)之FPGA電路如何在測試平台進行模擬驗證運算－ysy168twIQ的部落格

//===============================================================
// SD工作室 Verilog 教學eBOOK (Taiwan Version:01)
//---------------------------------------------------------------
// 網址:http://sanddservice.no-ip.org/
//---------------------------------------------------------------
// Module Name:JK_FF_example01_SD_Testbench.v
// 範例：Xilinx ISE 如何建立測試平台原始碼[Testbench Simulation 範例01]
// 目的:1.認識JK 正反器(Flip-Flop)之FPGA電路如何在測試平台進行模擬驗證運算
// 2.認識Verilog HDL Testbench[ISim]編寫應用
//===============================================================
`timescale 1ns / 1ps

module JK_FF_example01_SD_Testbench();
//TestBench通常input ports會改宣告成reg型態
//TestBench通常output ports會改宣告成wire型態
   reg J_t, K_t, CLK_t;
   wire Q_t, Qnot_t;

//Module to generate clock with period 2 time units
initial
begin
    forever
    begin
       CLK_t <= 1'b0;
       #1
       CLK_t <= 1'b1;
       #1
      CLK_t <= 1'b0;
    end
end

always
   //initial
begin
   {J_t,K_t} <= 2'b00;
   #1 $display("Q_t = %b,Qnot_t = %b", Q_t, Qnot_t);

   {J_t,K_t} <= 2'b01;
   #1 $display("Q_t = %b,Qnot_t = %b", Q_t, Qnot_t);

   {J_t,K_t} <= 2'b10;
   #1 $display("Q_t = %b,Qnot_t = %b", Q_t, Qnot_t);

   {J_t,K_t} <= 2'b11;
   #1 $display("Q_t = %b,Qnot_t = %b", Q_t, Qnot_t);
end

JK_FF_example01_SD jk_ff(J_t, K_t, CLK_t, Q_t, Qnot_t);

endmodule